06 Jul 1.(20    points)    We    found    that    the Â

1.(20    points)    We    found    that    the    instruction    fetch    and    memory    stages    are    the    critical    path    of    our    5-­‐stage    pipelined    MIPS    CPU.    Therefore,    we    changed    the    IF    and    MEM    stages    to    take    two    cycles    while    increasing    the    clock    rate.    You    can    assume    that    the    register    file    is    written    at    the    falling    edge    of    the    clock.Assume    that    no    pipelining    optimizations    have    been    made,    and    that    branch    comparisons    are    made    by    the    ALU.Here’s    how    our    pipeline    looks    when    executing    two    add    instructions:Clock    Cycle    #12345678add $t0, $t1, $t2IF1IF2IDEXMEM1MEM2WBadd $t3, $t4, $t5IF1IF2IDEXMEM1MEM2WBMake    sure    you    take    a    careful    look    at    the    above    diagram    before    answering    the    following    questions:1.(5points)    How    many    stalls    would    a    data    hazard    between    back-­‐to-­‐back    instructions    require?2.(5points)    How    many    stalls    would    be    needed    after    a    branch    instruction?3.Suppose    the    old    clock    period    was    150    ns    and    the    new    clockperiod    is    now    100ns.    Would    our    processor    have    a    significant    speedup    executing    a    large    chunk    of    code…i.(5points)    Without    any    pipelining    hazards?    Explain    your    answer    in    1-­‐2    sentences.ii.(5points)    With    50%    of    the    code    containing    back-­‐to-­‐back    data    hazards?    Explain    your    answer    in    1-­‐2    sentences.